1. Field of the Invention
This invention relates to a phase detector circuit for detecting the relative phase difference between two input signals.
2. Description of the Prior Art
Many applications of phase comparator or phase detector circuits utilize a feedback or servo system for locking the phase and frequency of one input to the phase and frequency of the other input which constitutes the reference signal in the system. An application is shown in FIG. 1 wherein it is illustrated that a phase detector circuit is utilized as a phase-locked-loop circuit. A phase detector circuit (1) compares the phase of an input signal S.sub.ig with the phase of a reference signal R.sub.ef, and produces an output signal related to the phase difference of the two signals. This output signal is transferred to a charge pump (2). The charge pump (2) responds to the output signal of the phase detector circuit and produces a control signal. The control signal is changed to a direct current by a low pass filter (3). The signal changed to the direct current controls the frequency of the output signal of a voltage-controlled oscillator (4). The frequency f.sub.v of the output signal of the voltage-controlled oscillator (4) is the output frequency f.sub.o of this system. The signal having the frequency f.sub.v is applied to a programmable divider (5), and the signal, which is derived from the programmable divider (5) having programmed dividing ratio N, is applied to the phase detector circuit (1). Thus, an output signal having the stable frequency f.sub.o can be derived from the phase-locked-loop circuit.
A circuit diagram of the phase detector circuit (1) and the charge pump (2) is shown in FIG. 2. FIG. 3 contains waveforms illustrating the operation of the circuit shown in FIG. 2. In FIG. 2, the reference signal R.sub.ef and the input signal S.sub.ig are applied to the phase detector circuit (1). Two inverters (6) and (7) invert the two signals. The output signal R.sub.ef of the inverter (6) is applied at the set input terminal of a flip-flop circuit (8) and the output signal S.sub.ig of the inverter (7) is applied at the set input terminal of a flip-flop circuit (9). The Q output signals S.sub.1 and S.sub.2 of the flip-flop circuits (8) and (9) are applied at the set input terminals of flip-flop circuits (10) and (11), respectively. The Q output signal S.sub.1 and S.sub.2 are also applied to a NAND gate 12. The NAND gate (12) has additional input terminals for receiving the output signals of the flip-flop circuits (10) and (11). The output signal of the NAND gate (12) is applied to AND gates of the flip-flop circuits (8) and (9) and resets the input terminals of the flip-flop circuits (10) and (11). The Q output signals P and N are applied to an AND gate (13). The Q output signals P and N become the output signals of the phase detector circuit (1). The output signals P and N of the phase detector circuit (1) are applied to the charge pump (2).
The charge pump (2) is constructed of a P-channel MOS transistor (14) and a N-channel MOS transistor (15) connected in series between a power supply V.sub.DD and ground. An inverter (16) is connected to the gate of the transistor (15) in order to provide a predetermined logic signal. The gate of the transistor (14) receives the output signal P of the flip-flop circuit (8) and the inverter (16) receives the output signal N of the flip-flop circuit (9). The charge pump (2) produces an output signal D.sub.o in response to the output signals of the phase detector circuit (1).
As shown in FIG. 3, when the phase of the input signal S.sub.ig is delayed more than the phase of the reference signal R.sub.ef, the Q output signal P of the flip-flop circuit (8) becomes ground level when the phase is delayed. When the phase of the input signal S.sub.ig is advanced as compared to the reference signal R.sub.ef, the Q output signal N of the flip-flop circuit (9) becomes ground level during this period. Consequently, the output signal D.sub.o of the charge pump (2) becomes the power supply level V.sub.DD during the period when the input signal S.sub.ig is delayed as compared to the reference signal R.sub.ef and becomes the ground level V.sub.ss during the period when the input signal S.sub.ig is advanced as compared to the reference signal R.sub.ef. Further, as illustrated in FIG. 3, when the phase of the input signal S.sub.ig is equal to that of the reference signal R.sub.ef, the output signal D.sub.o goes to a high impedance state.
The output signal LD of the AND gate (13) of the phase detector circuit (1) goes to ground level during the period that the phase of the input signal S.sub.ig is delayed or advanced as compared to the reference signal R.sub.ef, as illustrated in FIG. 3. The charge pump (2) in this circuit operates as a tristate buffer circuit (i.e., the output signal of the charge pump (2) will be the power supply level, the ground level or the high impedance state). In the phase-locked-loop circuit, this signal is transferred to the low pass filter.
FIG. 4 shows a logic diagram of the phase detector circuit illustrated in FIG. 2 and the numbers and marks in FIG. 4 correspond to those in FIG. 2. Further, a NAND gate which has two input terminals (17) and (18) is shown in FIG. 5 and it is constructed by complementary MOS transistors. The NAND gate produces at an output terminal (19) the signal of a power supply V.sub.DD level (high level) only when all input signals are high level. An inverter constructed by complementary MOS transistors is shown in FIG. 6. In this inverter, the input signal to the input terminal (20) is inverted and an inverted signal is produced at the output terminal (21).
Generally, if a logic gate is constructed by complementary MOS transistors, two MOS transistors are required for one input signal. The NAND gate in FIG. 5 requires four transistors for two input signals and the inverter requires two transistors for one input signal.
If the circuit in FIG. 4 is constructed by complementary MOS transistors, forty-eight transistors would be required.
Thus, the conventional circuit has disadvantages in that the transistors increase in number and the area where the circuit is formed becomes larger. Further, in the conventional circuit, as the two output signals of the flip-flop circuits (8) and (9) aren't in an inverse relationship with respect to each other, the inverter (16) is needed in order to obtain the signal N required in the charge pump (2). Thus, the transistors are further increased in number.